Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys

ABSTRACT

In an integrated circuit structure, the improvement comprising a wire bonded Cu-pad with Cu-wire component, wherein the Cu-pad Cu-wire component is characterized by self-passivation, low resistance, high bond strength, and improved resistance to oxidation and corrosion, the Cu-pad Cu-wire component comprising:  
     a metallization-line;  
     a liner separating the metallization line and a Cu-alloy surrounding a Cu-pad;  
     a dielectric surrounding the liner; and  
     a Cu-pad bonded to a Cu-alloy wire; the Cu-wire component being characterized by self-passivation areas on:  
     a) a dopant rich interface in between the Cu-alloy and liner;  
     b) a surface of the Cu-pad;  
     c) a surface of the bond between the Cu-pad and the Cu-alloy wire; and  
     d) a surface of the Cu-alloy wire.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to wire bonding of Cu-Pads with Cu-wiresusing self-passivating Cu-alloys. The self-passivation layer resultingfrom the dopant rich Cu-alloy protects the Cu from corrosion andoxidation.

[0003] 2. Description of Related Art

[0004] In the art of wirebonding, the current state of the art is to useAl-pads in combination with conventional Al-wedge or Au-ball bonding.However, the introduction of the Al-pads on top of a Cu basedmetallization is expensive and necessitates additional process steps.

[0005] Further, if contemporary bonding of the Cu-wires on Cu-pads isemployed, the exposed Cu layer would be highly susceptible corrosion andoxidation.

[0006] The prior art direct chip attachment with wirebonds onconventional overplated, overcoated copper (Cu) pads is costly becausecostly platings are required on circuit carriers possessing direct chipattach (DCA) wirebonded integrated circuit (IC) chips and wirebondjumper circuits to perform high yield wirebonding on carriers possessingcopper circuits. The IC chips are attached to the circuit carrier withan adhesive or solder chip attach material using heat. A circuitcovercoat or solder mask covers the copper circuits. In direct chipattach (DCA) wirebond operations, silicon chips are wirebonded tointerconnection pads on circuit carriers that possess a combination ofbarrier underplatings and noble or seminoble metal overplate finishes orsurface coatings. The common layered surface finish metallurgies forcircuit carrier wirebonding applications are of a nickel (Ni)underplating coating covered by a surface overplating coating layer ofgold (Au), palladium (Pd), or silver (Ag). These layered surface finishtreatments inhibit diffusion of underlying copper (Cu) circuitmetallization to the surface of the overplate and prevent subsequentoxidation of the wirebond pad surfaces. Considerable oxidation of padsurfaces prior to wirebonding can otherwise result in both inability towirebond with high yield and deterioration of wirebond interconnectionreliability. Use of these overplating treatments on copper pads has beenused to provide both high yield and high reliability wirebondinterconnections.

[0007] These plating treatments are costly, due to precious metalcontent and strict process controls required on plating bathchemistries. Further, when using electrolytic plating, bussingconfigurations must be provided to all areas requiring a platingtreatment. The bussing compromises more efficient wiring configurationsand can also prevent maximum usage of available carrier space in bothpanel and circuit designs. The electrolytic platings can result inhigher circuit piece price costs due to inefficient packing ofmulti-microprocessor circuit configurations on panelized carriermaterials including flexible carrier materials, such as polyimide,polyester, and rigid carrier materials, such as a glass epoxy compositeor ceramic, liquid crystal polymer (LCP).

[0008] U.S. Pat. No. 5,632,438 disclose a direct chip attachment processfor aluminum wirebonding on copper circuitization comprising: passingone integrated circuit chip to a carrier; applying to the carrier anattached integrated circuit chip an aqueous cleaning solution containingcitric and oxalic acid based additives; applying to the carrier andattached integrated circuit chip a rinse; and wirebonding on coppercircuitization carried by the carrier.

[0009] A method for improving bond ability for deep-submicron integratedcircuit packages is disclosed in U.S. Pat. No. 6,110,816. The methodcomprises: providing a semiconductor substrate having a top electricallyconducting layer, and an overlying layer covering the top electricallyconducting layer, and a photoresist applied to the overlying layer;patterning the photoresist to form an array of submicron size holes;etching openings through the overlying layer to the top electricallyconducting layer, and forming a rough textured surface profile in thetop electrically conducting layer through the opening of the overlyinglayer; and depositing a passivation film over the overlying layer andforming wiring pad windows for wire ball bonding.

[0010] In the art area of wirebonding of Cu-pads with Cu-wires formaking integrated circuits, pure Cu-wire bonded to pure Cu-pads providesthe best quality bond and lowest resistance; however, pure Cu does notprovide a self-passivation effect, and therefore leaves the Cu at perilto corrosion and oxidation. Accordingly, there is a need in this art toprovide Cu-wire bonded on Cu-pads so as to provide good bondability andgood bond quality coupled with the capacity of self-passivation so as toenable the copper and integrated circuit formed from this fabrication toachieve self-passivation, and thereby resist corrosion and oxidation.

SUMMARY OF THE INVENTION

[0011] One object of the present invention is to provide Cu-wire bondedto Cu-pads in a manner so as to provide good bond quality and lowresistance, in which the Cu is characterized by self-passivation.

[0012] Another object of the present invention is to provide Cu-wirebonded on Cu-pads in a manner so as to provide good bond quality and lowresistance, whereby the Cu-wire bonded on Cu-pads is resistant tocorrosion and oxidation due to use of self-passivating Cu-alloys.

[0013] A further object of the present invention is to provide Cu-wirebonded on Cu-pads to provide good bond quality and lower resistance, byusing Cu-wire and Cu-pads fabricated to 100% out of Cu-alloys, toprovide Cu-wire bonded to Cu-pads, where the Cu is resistant tocorrosion and oxidation due to use of self-passivating Cu-alloys.

[0014] A yet further object of the present invention is to provide,Cu-wire bonded to Cu-pads, in which the wire is either a solid Cu-alloywire or a bi-layer Cu-wire, with an inner core consisting of theCu-alloy and the outer core being pure Cu, so as to provide goodbondability and bond quality upon bonding the copper wire to Cu-pads, toachieve self-passivation from the Cu-alloy.

[0015] A further object yet still of the present invention is to provideCu-wire bonded to Cu-pads wherein the Cu-wire is a bilayer and theCu-pad is a bi-layer (Cu-alloy seed layer+pure Cu-fill) to achieveself-passivation and therefore resistance to corrosion and oxidation.

[0016] In accordance with the invention good bondability and good bondquality coupled with resistance to corrosion and oxidation is obtainedwhen wire bonding of Cu-pads with Cu-wires is performed using Cu-alloys(Cu-Al, Cu-Mg, and Cu-Li).

BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0017]FIG. 1 shows a Cu-alloy wire prior to bonding with a Cu-pad, inwhich the Cu pad is surrounded by a Cu-alloy, which is surrounded by aliner, all of which is disposed in a dielectric.

[0018]FIG. 2 shows a Cu-alloy wire after wirebonding and annealing to aCu-pad, in which the formed bond is either a ball or wedge, and in whichthere is a dopant rich interface layer characterized byself-passivation, as shown by the X's.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0019] In general, in the context of the invention, the wirebonding ofCu-pads with Cu-wires using self-passivating Cu-alloys for making asemiconductor device or integrated circuit is prepared by the followingprocess sequence:

[0020] a) Patterning a (dual-) damascene structure in dielectric to formthe wiring and the bond pads;

[0021] b) Depositing a metallic liner (PVD, CVD, electroless, or otherart known method (this step may be optional by using the optimum amountof Cu-alloy);

[0022] c) Depositing Cu-alloy as seed-layer for final Cu-fill (PVD, CVDor other known art methods);

[0023] d) Fill of damascene structure with pure Cu (electroplating, CVD,electroless, PVD or other art known methods);

[0024] e) Pre-CMP anneal at low temperatures (<200° C.), to form a lowresistive Cu film with large Cu grains; however, out-diffusion of thedopants in the Cu-alloy should be suppressed at this point;

[0025] f) Cu-CMP to remove the Cu-overfill, followed by liner CMP.

[0026] The four possible options for the subsequent process sequence areas follows:

[0027] Option A:

[0028] 7) Post CMP anneal (temperature range: 250° C. to 450° C.) toform the self-passivating dopant rich layer at the Cu-surface and at theCu-liner interface (it is beneficial to start with a gradual temperatureincrease to suppress hillock formation. After the initial formation of adopant-rich surface layer the hillock formation is significantlyreduced);

[0029] 8) Depositing the dielectric cap layer (Cu-diffusion barrier,Si-Nitride, Blok or other art known methods). It is possible toeliminate this dielectric diffusion barrier totally and continue theprocessing with SiO₂ deposition or the deposition of other dielectricmaterials (e.g. low k materials).

[0030] Option B:

[0031] 7) Depositing of dielectric cap layer (Cu diffusion barrier,Si-Nitride, Blok or other art known methods);

[0032] 8) Annealing (temperature range: 250° C.-450° C.) to formself-passivating dopant rich layer at the Cu-dielectric cap layerinterface and at the Cu-liner interface.

[0033] Option C:

[0034] 7) Post CMP annealing in a temperature range: 250° C.-400° C.,this temperature is lower when compared to 9). The post cap layer annealis approximately 50° C. to form a partially self-passivating dopant richlayer at the Cu-surface and at the Cu-liner interface. It is beneficialto start with a gradual temperature increase to suppress hillockformation. After the initial (partial) formation of a dopant-richsurface layer the hillock formation is significantly reduced;

[0035] 8) Depositing of the dielectric cap layer (Cu diffusion barrier,Si-Nitride, Blok or other art known methods). It is possible toeliminate this dielectric diffusion barrier totally and continue theprocessing with SiO₂ deposition or the deposition of other dielectricmaterials (e.g. low k materials);

[0036] 9) Post cap layer annealing (temperature range: 300° C.-450° C.,approximately 50° C. higher than 7) post CMP anneal, to form the finalself-passivation layer on the liner and cap layer interface. Thisapproach with the two anneal steps 7) and 8) is beneficial with respectto hillock formation and adhesion.

[0037] Option D:

[0038] 7) Depositing the dielectric cap layer (Cu diffusion barrier,Si-Nitride, Blok or other art known methods). No anneal and therefore noformation of the self-passivating layer at this point of the processsequence.

[0039] The next steps are the key steps of this invention process:

[0040] 10) Depositing of a final passivation layer (oxide/nitridecombinations);

[0041] 11) Deposition of a polyimide or photo-sensitive polyimide (PSPI)layer (optional);

[0042] 12) Patterning of the polyimide (or PSPI) and the finalpassivation (including the dielectric cap layer on top of the Cu) bylithographic and etch steps to open the pad area. During the pad openingetch (+post treatments) the self-passivating layer at the Cu/cap layerinterface is removed in order to have a clean Cu surface for probing;

[0043] 13) Probing the chips;

[0044] 14) Wirebonding (wedge or ball bonding) of the probed pads withthe Cu-alloy wires; and

[0045] 15) Annealing the bonded chips at temperatures between 250°C.-450° C. to form the self-passivating layer on the open Cu-pad surfaceand on the Cu-wire.

[0046] In between the probing step 13) and bonding step 14), a longertime elapses. In order to protect the Cu-pads during this time, anadditional step may be introduced to form theself-passivating/protective layer on the probed Cu surface. Shortlybefore bonding, this layer is removed by wet cleans in order to have aclean Cu-pad surface for optimum bond quality.

[0047] Reference is now made to FIG. 1, which depicts a Cu-alloy wire 10prior to bonding with the Cu-pad 11. The Cu-pad is surrounded by aCu-alloy 12, which in turn is separated from the dielectric 13 by aliner 14.

[0048] Optionally, as shown by the dotted lines, a polyimide 15 may bedeposited on top of the dielectric.

[0049] As may be seen from FIG. 2, after wirebonding followed byannealing, the passivated dopant rich interface layer 16 andself-passivated Cu-surface 17, both of which are designated by X's areformed. The self passivation is around the Cu-alloy, around the bondball or wedge 18, and at the juncture of the pad and wire joinings. Thisdopant rich self-passivating layer is free from hillock structures andprotects the Cu from corrosion, oxidation and out-diffusion of Cu intothe surrounding semiconductor device areas.

[0050] In the context of the invention, the Cu-alloys may be Cu-Al,Cu-Mg, Cu-Li as well as other well-known Cu-alloys, and theconcentration of the non-Cu doping material from the other component ofthe Cu-alloy will range from about 0.1 to about 5.0% atomic weightpercent of the Cu-alloy.

[0051] Wirebonding of Cu-pads with Cu-wires using self-passivatingCu-alloys is particularly important for improving bondability coupledwith protecting the Cu from corrosion and oxidation by virtue of theself-passivation induced by the invention process.

[0052] Accordingly, the Cu-pads with Cu-wires using self-passivatingCu-alloys provides comparable bond quality and low resistance to pureCu-wire bonded on pure Cu-pads and also provides the self-passivationeffect not obtained with pure Cu-wire bonded on pure Cu-pads. Stateddifferently, the bi-layer Cu-wire in combination with a bi-layer Cu-pads(Cu-alloy seed-layer+pure Cu-fill) exhibits optimum characteristics ofself-passivation+low resistance and high bond strength.

[0053] While certain representative embodiments and details have beenshown for purposes of illustrating preferred embodiments of theinvention, it will be apparent to those skilled in the art that variouschanges in the invention disclosed may be made without departing fromthe spirit and scope of the invention, which is defined in the appendedclaims.

I claim:
 1. In an integrated circuit structure, the improvementcomprising a wire bonded Cu-pad Cu-wire component, wherein said Cu-padCu-wire component is characterized by self-passivation, low resistance,high bond strength, and improved resistance to oxidation and corrosion,said Cu-pad Cu-wire component comprising: a metallization-line; a linerseparating said metallization line and a Cu-alloy surrounding a Cu-pad;a dielectric surrounding said liner; and a Cu-pad bonded to a Cu-alloywire; and said Cu-wire component being characterized by self-passivationareas on: a) a dopant rich interface between the Cu-alloy and liner; b)a surface of said Cu-pad; c) a surface of a bond between said Cu-pad andsaid Cu-alloy wire; and d) a surface of said Cu-alloy wire.
 2. Thestructure of claim 1 wherein a passivation layer of an oxide, nitride orcombinations of nitrides have been deposited on said dielectric followedby annealing at a temperature of from about 250° C. to about 450° C. 3.The structure of claim 2 wherein said passivation areas is present in arange of from 0.1 to about 5.0 atomic weight percent of said Cu-alloy.4. The structure of claim 3 wherein said Cu-alloy is selected from thegroup consisting of Cu-Al, Cu-Mg and Cu-Li.
 5. The structure of claim 4wherein said Cu-alloy is Cu-Al.
 6. The structure of claim 4 wherein saidCu-alloy is Cu-Mg.
 7. The structure of claim 4 wherein said Cu-alloy isCu-Li.
 8. In a process of preparing an integrated circuit structurecomprising a wire bonded Cu-pad with Cu-wire component, the improvementwherein a self-passivated Cu-pad Cu-wire is characterized by resistanceto oxidation and corrosion and improved adhesion in an interface betweensaid Cu-pad and metallization lines and between said Cu-pad and a bondjoining a Cu-alloy wire, comprising: a) patterning a damascene structurein a dielectric to form wiring and bond pads; b) depositing a metallicliner; c) depositing Cu-alloy as seed-layer for final Cu-fill; d)filling said damascene structure with pure Cu; e) pre-CMP annealing atlow temperatures (<200° C.), to form a low resistive Cu film with largeCu grains; and prevent out-diffusion of dopants in the Cu-alloy; f)Cu-CMP to remove Cu-overfill, and by liner CMP; g) post CMP annealing ata temperature range of from about 250° C. to about 450° C. to form aself-passivating dopant rich layer at the Cu-surface and at the Cu-linerinterface; h) depositing a polyimide layer; i) patterning of thepolyimide and completing passivation by lithographic and etch steps toopen the pad area to provide a clean Cu surface for probing; j) probingthe chips; k) wirebonding of the probed pads with the Cu-alloy wires;and l) annealing the bonded chips at temperatures between about 250° C.to about 450° C. to form a self-passivating layer on the open Cu-padsurface and on the Cu-wire.
 9. The process of claim 8 wherein, afterstep a), step b) is eliminated by depositing an optimum amount ofCu-alloy.
 10. In a process of preparing an integrated circuit structurecomprising a wire bonded Cu-pad with Cu-wire component, the improvementwherein a self-passivated Cu-pad Cu-wire is characterized by resistanceto oxidation and corrosion and improved adhesion in an interface betweensaid Cu-pad and metallization lines and between said Cu-pad and a bondjoining a Cu-alloy wire, comprising: a) patterning a damascene structurein a dielectric to form wiring and bond pads; b) depositing a metallicliner; c) depositing Cu-alloy as seed-layer for final Cu-fill; d)filling said damascene structure with pure Cu; e) pre-CMP annealing atlow temperatures (<200° C.), to form a low resistive Cu film with largeCu grains; and prevent out-diffusion of dopants in the Cu-alloy; f)Cu-CMP to remove Cu-overfill, and by liner CMP; g) depositing adielectric cap layer; h) annealing at a temperature of from about 250°C. to about 450° C. to form a self-passivating dopant rich layer at theCu-dielectric cap interface and at the Cu-liner interface; i) depositinga polyimide layer; j) patterning of the polyimide and completingpassivation by lithographic and etch steps to open the pad area toprovide a clean Cu surface for probing; k) probing the chips; l)wirebonding of the probed pads with the Cu-alloy wires; and m) annealingthe bonded chips at temperatures between about 250° C. to about 450° C.to form a self-passivating layer on the open Cu-pad surface and on theCu-Wire.
 11. The process of claim 10 wherein, after step a); step b) iseliminated by depositing an optimum amount of Cu-alloy.
 12. In a processof preparing an integrated circuit structure comprising a wire bondedCu-pad with Cu-wire component, the improvement wherein a self-passivatedCu-pad Cu-wire is characterized by resistance to oxidation and corrosionand improved adhesion in an interface between said Cu-pad andmetallization lines and between said Cu-pad and a bond joining aCu-alloy wire, comprising: a) patterning a damascene structure in adielectric to form wiring and bond pads; b) depositing a metallic liner;c) depositing Cu-alloy as seed-layer for final Cu-fill; d) filling saiddamascene structure with pure Cu; e) pre-CMP annealing at lowtemperatures (<200° C.), to form a low resistive Cu film with large Cugrains; and prevent out-diffusion of dopants in the Cu-alloy; f) Cu-CMPto remove Cu-overfill, and by liner CMP; g) post CMP annealing at atemperature of from about 250° C. to about 400° C. to form a partiallyself-passivating dopant rich layer at the Cu-surface and at the Cu-linerinterface; h) depositing a dielectric cap layer; i) post cap layerannealing at a temperature of from about 300° C. to about 450° to form afinal self-passivation layer on the liner and cap layer interface; j)depositing a polyimide layer; k) patterning of the polyimide andcompleting passivation by lithographic and etch steps to open the padarea to provide a clean Cu surface for probing; l) probing the chips; m)wirebonding of the probed pads with the Cu-alloy wires; and n) annealingthe bonded chips at temperatures between 250° C. to about 450° C. toform a self-passivating layer on the open Cu-pad surface and on theCu-Wire.
 13. The process of claim 12 wherein, after step a); step b) iseliminated by depositing an optimum amount of Cu-alloy.
 14. In a processof preparing an integrated circuit structure comprising a wire bondedCu-pad with Cu-wire component, the improvement wherein a self-passivatedCu-pad Cu-wire is characterized by resistance to oxidation and corrosionand improved adhesion in an interface between said Cu-pad andmetallization lines and between said Cu-pad and a bond joining aCu-alloy wire, comprising: a) patterning a damascene structure in adielectric to form wiring and bond pads; b) depositing a metallic liner;c) depositing Cu-alloy as seed-layer for final Cu-fill; d) filling saiddamascene structure with pure Cu; e) pre-CMP annealing at lowtemperatures (<200° C.), to form a low resistive Cu film with large Cugrains; and prevent out-diffusion of dopants in the Cu-alloy; f) cu-CMPto remove Cu-overfill, and by liner CMP; g) post CMP annealing at atemperature range of from about 250° C. to about 450° C. to form aself-passivating dopant rich layer at the Cu-surface and at the Cu-linerinterface; h) depositing a dielectric cap layer; i) depositing apolyimide layer; j) patterning of the polyimide and completingpassivation by lithographic and etch steps to open the pad area toprovide a clean Cu surface for probing; k) probing the chips; l)wirebonding of the probed pads with the Cu-alloy wires; and m) annealingthe bonded chips at temperatures between about 250° C. to about 450° C.to form a self-passivating layer on the open Cu-pad surface and on theCu-wire.
 15. The process of claim 15 wherein, between after step a),step b) is eliminated by depositing an optimum amount of Cu-alloy. 16.The structure of claim 1 wherein said Cu-pad is a Cu-alloy.
 17. Thestructure of claim 1 wherein said Cu-wire is a bilayer with an innercore of Cu-alloy and on outer area of pure Cu, and said Cu-pad is aCu-alloy.
 18. The structure of claim 1 wherein said Cu-wire is Cu-alloyand said Cu-pad is Cu-alloy.